Number of hours
- Lectures 1.5
- Projects 15.0
- Tutorials -
- Internship -
- Laboratory works 15.0
- Written tests -
ECTS
ECTS 3.0
Goal(s)
Filling the gap between high level programming and computer architecture, it provides students with a synthesis of these fields and a global understanding of how computers work. The course is organized around the learning of assembly languages (RISC).
The student will understand how a processor work, designing a RISC processor.
Responsible(s)
Lionel RIEG
Content(s)
- Introduction. Processors. Computers. Programming model
- Instructions coding
- Symbolic representation
- Assembler directives
- Translation of control structures
- Representation of data structures
- Procedures and functions. Linking conventions and stack organization. Local variables.
- Design of RISC processor (using Finite State Machine that controls a data path to complete)
- Interrupts
Working knowledge of the C language and of the basis of computer architecture
Test
NPR : Project evaluation
NTP : Practice session evaluation
NE : Final exam
N = (NPR+NTP+NE)/3
- MCC en présentiel et distanciel **
NPR : note de projet CP
NTP : note de TP EP
NEx : note de l'examen de la session x (1 ou 2)
N1 = (NPR+NTP+NE1)/3
N2 = (NPR+NTP+NE2)/3
- MCC en présentiel et distanciel **
Calendar
The course exists in the following branches:
- Curriculum - Core curriculum - Semester 6
Additional Information
Course ID : 3MMCEP
Course language(s): 
The course is attached to the following structures:
You can find this course among all other courses.
Bibliography
Le langage VHDL : du langage au circuit, du circuit au langage / Jacques Weber, Sébastien Moutault, Maurice Meaudre
The RISC-V Instruction Set Manual, Volume I: Unprivileged ISA (https://riscv.org/technical/specifications/)