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Informatique et Mathématiques appliquées
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> Formation > Cursus ingénieur

Transaction level modeling of systems on chip - 5MMMTSP

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  • Number of hours

    • Lectures : 15.0
    • Laboratory works : 9.0
    ECTS : 3.0

Goals

To cope with the complexity of the development of modern systems-on-chip, the industry utilizes abstractions such as transaction-level models. These models are generally written with the help of SystemC.

In this course, the students will learn the principles of transaction-level modeling in SystemC. The various abstraction levels at which a model may be written and the different ways to integrate embedded software in the models will also be discussed.

Contact Frédéric PETROT

Content

  • Short introduction to C++
  • Presentation of SystemC
  • The TLM-2 library
  • Modeling issues, faithfulness of TLM models.
  • Integration of the embedded software in a TLM platform
  • Lab works


Prerequisites
  • Concepts of computer architecture
  • Programming in C

A knowledge of C++ is appreciable.

Tests

written exam + labs



N1=(E1 + TP)/2
N2=(E2 + TP)/2

Additional Information

Curriculum->Embedded Systems & Connect. Devices->Semester 9

Bibliography

1. Frank Ghenassia, Transaction-Level Modeling with SystemC: TLM Concepts and Applications for Embedded Systems, 1st ed. (Springer, 2005).

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Date of update January 15, 2017

Grenoble INP Institut d'ingénierie Univ. Grenoble Alpes