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Number of hours
Lectures : 16.5
Tutorials : 16.5
ECTS : 2.5
This course aims at presenting the advanced hardware mechanisms that are used for optimized program execution in computers. These mechanisms allow to drastically increase processor and memory subsystem performance, and are also required to understand on chip or on board communication infrastructure. Other hardware mechanisms are necessary to understand more system related problems, such as parallel programming and virtual memory handling in operating systems.
Contact Frédéric PETROT
Bus infrastructure : notion of master, slave, arbiter
RISC processor architecture study, based on the R3000
Caches, design and policies
Virtual memory support, TLB, MMU
Multiprocessor SMP/MP, hardware support for cache coherency and memory consistency, locks engines
Digital circuits and computer architecture elements and Assembly language programming Modules
one written exam (3 h). If failed, a second 2h exam.