Number of hours
- Lectures 18.0
- Laboratory works 36.0
ECTS
ECTS 2.5
Goal(s)
This module aims at presenting the main concepts, methods and tools used in design, validation and test of digital integrated systems.
By nature, this module requires a large part of practical works. It therefore includes lab sessions allowing practicing with the main tools in the design flow.
Contact Régis LEVEUGLE
Content(s)
Lectures
Importance of integration for embedded systems.
Design flow and evolution, basics on high-level synthesis.
VHDL modelling for synthesis and re-use.
Functional and timing verification.
Principles of test vector generation and design for testability.
Implementation optimization and verification.
Lab sessions
Specification, implementation, and verification of a custom cell-based digital circuit.
Prerequisites
Logic design, basic concepts in computer architecture, notions in VHDL-based modelling.
Test
Final exam (2h) and reports on practical works
N1=1/2E1+1/2CR
N2=1/2E2+1/2CR Maintien de la note de compte-rendu du TP
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