Number of hours
- Lectures 16.5
- Laboratory works 33.0
ECTS
ECTS 3.0
Goal(s)
This module aims at presenting the main concepts, methods and tools used in design, validation and test of digital integrated systems.
By nature, this module requires a large part of practical works. It therefore includes lab sessions allowing practicing with the main tools in the design flow.
Content(s)
Lectures
Importance of integration for embedded systems.
Design flow and evolution, basics on high-level synthesis.
VHDL modelling for synthesis and re-use.
Functional and timing verification.
Principles of test vector generation and design for testability.
Implementation optimization and verification.
Lab sessions
Specification, implementation, and verification of a custom cell-based digital circuit.
Prerequisites
Logic design, basic concepts in computer architecture, notions in VHDL-based modelling.
Test
Final exam (2h) and reports on practical works
N1= 50% rapport de TP, 50% note de DS
Toute absence et retard lors des séances de TP est automatiquement pris en compte dans la note du rapport.
N2=50% note de TP non rattrapable, 50% note de DS session 2