- 4MMARCHP

Goal(s)

This course aims at presenting the advanced hardware mechanisms that are used for optimized program execution in computers. These mechanisms allow to drastically increase processor and memory subsystem performance, and are also required to understand on chip or on board communication infrastructure. Other hardware mechanisms are necessary to understand more system related problems, such as parallel programming and virtual memory handling in operating systems.

Responsible(s)

Julie DUMAS

Content(s)

Bus infrastructure : notion of master, slave, arbiter
RISC processor architecture study, based on the R3000
Caches, design and policies
Virtual memory support, TLB, MMU
Multiprocessor SMP/MP, hardware support for cache coherency and memory consistency, locks engines
Detailed presentation of hardware acceleration techniques used in processor architectures such as x86-64, ARM Axx, Power, etc.

Out-of-order execution, scheduling
Register renaming
Speculation techniques: branch prediction, value prediction
Presentation of hidden channel attacks such as spectre/meltdown
VLIW architectures for power efficiency
SIMD extensions for exploiting programs fine grain parallelism

Digital circuits and computer architecture elements and Assembly language programming Modules

Test

Evaluation : Examen écrit (2h)

Resit : Examen écrit (2h)

N1 = ET1
N2 = Max(ET1,ET2)

REGULAR EXAM SESSION:
Exam type: one paper-based exam
Duration: 2 hours (extended time: 2 hours 40 minutes)
Permitted materials: all
Prohibited materials: none
Equipment:
Permitted equipment: none
Prohibited equipment: all

MAKE-UP SESSION:
Exam type: one paper-based exam
Duration: 2 hours (extended time: 2 hours 40 minutes)
Permitted materials: all
Prohibited materials:
Equipment:
Permitted equipment: none
Prohibited equipment: all

Calendar

The course exists in the following branches:

• Curriculum - Core curriculum - Semester 8

Additional Information

Course ID : 4MMARCHP
Course language(s):

You can find this course among all other courses.

Bibliography

David Patterson et John Hennessy, Computer Architecture, A Quantitative Approach, 4ème édition, Morgan Kaufman (Turing award 2017)
William Stallings, Computer Organization and Architecture, 5ème édition, Prentice-Hall
"Modern Processor Design: Fundamentals of Superscalar Processors", J-P. Shen and M. Lipasti.