Aller au menu Aller au contenu
Une voie, plusieurs choix
Informatique et Mathématiques appliquées
Une voie, plusieurs choix

> Formation > Cursus ingénieur

Low-level software and hardware - 3MMCEP

A+Augmenter la taille du texteA-Réduire la taille du texteImprimer le documentEnvoyer cette page par mail cet article Facebook Twitter Linked In
  • Number of hours

    • Lectures : 3.0
    • Tutorials : -
    • Laboratory works : 15.0
    • Projects : 15.0
    • Internship : -
    • Written tests : -
    ECTS : 3.0
  • Officials : Olivier MULLER

Goals

Filling the gap between high level programming and computer architecture, it provides students with a synthesis of these fields and a global understanding of how computers work. The course is organized around the learning of assembly languages (RISC and CISC).

The student will understand how a processor work, designing a RISC processor.

Content

  • Introduction. Processors. Computers. Programming model
  • Instructions coding
  • Symbolic representation
  • Assembler directives
  • Translation of control structures
  • Representation of data structures
  • Procedures and functions. Linking conventions and stack organization. Local variables.
  • Design of RISC processor (using Finite State Machine that controls a data path to complete)
  • Interrupts

Prerequisites

Knowledge of a classical imperative language (Ada, C...) and of the basis of computer architecture

Tests

NPR : Project evaluation (authorized only one manuscript A4 recto/verso)
NTP : Practical final examination
NTP2 : Practical final examination for session 2

N1 = (NPR+2*NTP)/3
N2 = NTP2

Calendar

The course exists in the following branches:

  • Curriculum - Core curriculum - Semester 6
see the course schedule for 2020-2021

Additional Information

Course ID : 3MMCEP
Course language(s): FR

The course is attached to the following structures:

You can find this course among all other courses.

Bibliography

Le langage VHDL : du langage au circuit, du circuit au langage / Jacques Weber, Sébastien Moutault, Maurice Meaudre
SYSTEM V APPLICATION BINARY INTERFACE MIPS RISC Processor

A+Augmenter la taille du texteA-Réduire la taille du texteImprimer le documentEnvoyer cette page par mail cet article Facebook Twitter Linked In

Date of update January 15, 2017

Université Grenoble Alpes